Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries
Sridhar, Mahankali ; Raj, Arvind ; Vincenzi, Alessandro ; Ruggiero, Martino ; Brunschwiler, Thomas ; Atienza Alonso, David.
Presented at: The 16th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC’10), Barcelona, Spain, 6-8 October, 2010.
Published in: Proceedings of the 16th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC’10), vol. 1, num. 1, 2010, p. pp. 5 – 11. New York: IEEE Press, 2010.
The advent of 3D stacked ICs with accumulating heat fluxes stresses thermal reliability and is responsible for temperature driven performance deterioration of the electronic systems Hot spots with power densities typically rising up to 250 W/cm2 are not acceptable, with the result of limited performance improvement in next generation high performance microprocessor stacks. Unfortunately traditional back-side cooling only scales with the chip stack footprint, but not with the number of tiers. Direct heat removal from the IC dies via inter-tier liquid cooling is a promising solution to address this problem. In this regard, a thermal-aware design of a 3D IC with liquid cooling for optimal electronic performance and reliability requires fast modelling and simulation of the liquid cooling during the early stages of the design. In this paper, we propose a novel compact transient thermal modelling (CTTM) scheme for liquid cooling in 3D ICs via microchannels and enhanced heat transfer cavity geometries such as pin-fin structures. The model is compatible with the existing thermal- CAD tools for ICs and offers significant speed-up over commercial computational fluid dynamics simulators (13478x for pin-fin geometry with 1.1% error in temperature). In addition, the model is highly flexible and it provides a generic framework in which heat transfer coefficient data from numerical simulations or existing correlations can be incorporated depending upon the speed/accuracy needs of the designer. We have also studied the effects of using different techniques for the estimation of heat transfer coefficients on the accuracy of the model. This study highlights the need to consider developing flow conditions to accurately model the temperature field in the chip stack. The use of correlation data from fully developed flows only results in temperature error as high as 9 K (about 41%) near the inlet.
