Publications
The results and findings of PRO3D are published in :
- National and international journals;
- International and local conferences;
- Special issues of jrounals and chapters of edited books;
- International and national workshops and conferences.
There are currently 117 publications.
Lothar Thiele, Lars Schor, Iuliana Bacivarov, and Hoeseok Yang.
ACM Transactions in Embedded Computing Systems (TECS), March 2013.
High computational performance in multiprocessor system-on-chips (MPSoCs) is constrained by the ever-increasing power densities in integrated circuits, so that nowadays MPSoCs face various thermal issues. For instance, high chip temperatures may lead to long-term reliability concerns and short-term functional errors. Therefore, the new challenge in designing embedded real-time MPSoCs is to guarantee the nal performance and correct function of the system, considering both functional and non-functional properties. One way to achieve this is by ruling out mapping alternatives that do not fulfill requirements on performance or peak temperature already in early design stages. In this article, we propose a thermal-aware optimization framework for mapping realtime applications onto MPSoC platforms. The performance and temperature of mapping candidates are evaluated by formal temporal and thermal analysis models. To this end, analysis models are automatically generated during design space exploration, based on the same specifications as used for software synthesis. The analysis models are automatically calibrated with performance data reflecting the execution of the system on the target platform. The data is automatically obtained prior to design space exploration based on a set of benchmark mappings. Case studies show that the performance and temperature requirements are often conflicting goals and optimizing them together leads to major benefits in terms of a guaranteed and predictable high performance.
March 3rd, 2013 in
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Pratyush Kumar, Devesh Chokshi, and Lothar Thiele.
In In Proceedings of the 2013 Design, Automation & Test in Europe Conference & Exhibition, DATE 2013, Grenoble, France, March 2013. IEEE.
We study the problem of assigning speeds to resources serving distributed applications with delay, buff er and energy constraints. We argue that the considered problem does not have any straightforward solution due to the intricately related constraints. As a solution, we propose using Real-Time Calculus (RTC) to analyse the constraints and a SATis fiability solver to efficiently explore the design space. To this end, we develop an SMT solver by using the OpenSMT framework and the modular Performance Analysis (MPA) toolbox. Two key enablers for this implementation are the analysis of incomplete models and generation of conflict clauses in RTC. The results on problem instances with very large decision spaces indicate that the proposed SMT solver performs very well in practice.
March 3rd, 2013 in
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David Atienza Alonso.
In Platform 2012/STHORM Embedded Many-Core Acceleration (2nd P2012 Dev. Conf.). Diego Melpignano, Luca Benini, and Fabien Clermidy, editors. March 2013. DATE 2013 Workshop, Grenoble, France. http://www.date-conference.com/conference/workshop-w4.
March 3rd, 2013 in
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Saddek Bensalem, Marius Bozga, Ayoub Nouri, Julien Mottin, and Francois Pacull.
In Platform 2012/STHORM Embedded Many-Core Acceleration (2nd P2012 Dev. Conf.). Diego Melpignano, Luca Benini, and Fabien Clermidy, editors. March 2013. DATE 2013 Workshop, Grenoble, France. http://www.date-conference.com/conference/workshop-w4.
We present recent developments on implementation of parallel applications using the BIP design flow and the Multicore Communication API (MCAPI) implementation and its associated runtime for P2012/STHORM platform. The BIP design flow is actually being used for evaluation and prototype implementation of industrial-size parallel applications proposed in the context of several research projects. We shall demonstrate few of them, including HMAX Models, a video processing application for object recognition and AESA, a radar processing chain.
March 3rd, 2013 in
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Lars Schor, Hoeseok Yang, Iuliana Bacivarov, and Lothar Thiele.
In Formal Methods for Components and Objects, 10th International Symposium FMCO 2011. State-of-the-Art Survey. Bernhard Beckert, Ferruccio Damiani, Frank de Boer, and Marcello Bonsangue, editors. volume 7542 of LNCS. Springer, 2013.
The reduced feature size of electronic systems and the demand for high performance lead to increased power densities and high chip temperatures, which in turn reduce the system reliability. Thermal-aware task allocation and scheduling algorithms are promising approaches to reduce the peak temperature of multi-core systems with real-time constraints. However, as long as the worst case chip temperature is not incorporated into system analysis, no guarantees on the performance can be given. This paper explores thermal-aware task assignment strategies for real-time applications with non-deterministic workload that are running on a multi-core system. In particular, tasks are assigned to the multi-core system so that the worst-case chip temperature is minimized and all real-time deadlines are met. Each core has its own clock domain and the static assigned frequency corresponds to the minimum operation frequency such that no real-time deadline is missed. Finally, we show that the proposed temperature minimization problem can eciently be solved by metaheuristics.
January 3rd, 2013 in
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Francesco Zanini, David Atienza Alonso, Colin Jones, Luca Benini, and Giovanni De Micheli.
ACM Transactions on Design Automation of Electronic Systems, 18(1):1-24, 2013.
With technological advances, the number of cores integrated on a chip is increasing. This, in turn is leading to thermal constraints and thermal design challenges. Temperature gradients and hotspots not only affect the performance of the system, but also lead to unreliable circuit operation and a ect the life-time of the chip. Meeting temperature constraints and reducing hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. In this article we analyze the use of four of the most promising families of online control techniques for thermal management of multi-processors system-on-chip (MPSoC). In particular, in our exploration we aim at achieving an online smooth thermal control action that minimizes the performance loss as well as the computational and hardware overhead of embedding a thermal management system inside the MPSoC. The definition of the optimization problem to tackle in this work considers the thermal pro le of the system, its evolution over time and current time-varying workload requirements. Thus, this problem is formulated as a finite-horizon optimal control problem and we analyze the control features of different on-line thermal control approaches. In addition, we implemented the policies on an MPSoC hardware simulation platform and performed experiments on a cycle-accurate model of the 8-core Niagara multi-core architecture using benchmarks ranging from web-accessing to playing multimedia. Results show different trade-off s among the analyzed techniques regarding the thermal profile, the frequency setting, the power consumption and the implementation complexity.
January 3rd, 2013 in
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Ananda Basu, Saddek Bensalem, Marius Bozga, Paraskevas Bourgos, Mayur Maheshwari, and Jospeh Sifakis.
In Formal Methods for Components and Objects, 10th International Symposium FMCO 2011. State-of-the-Art Survey. Bernhard Beckert, Ferruccio Damiani, Frank de Boer, and Marcello Bonsangue, editors. volume 7542 of LNCS. Springer, 2013.
We present a component-based software design flow for building parallel applications running on top of manycore platforms. The flow is based on the BIP – Behaviour, Interaction, Priority – component
framework and its associated toolbox. It provides full support for modeling of application software, validation of its functional correctness, modeling and performance analysis on system-level models,
code generation and deployment on target manycore platforms. The paper details some of the steps of the design flow. The design flow is illustrated through the modeling and deployment of two
applications, the Cholesky factorization and the MJPEG decoding on MPARM, an ARM-based manycore platform. We emphasize the merits of the design flow, notably fast performance analysis
as well as code generation and efficient deployment on manycore platforms.
January 3rd, 2013 in
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Sylvain Durand, Suzanne Lesecq, Edith Beigne, Christian Fabre, Lionel Vincent, and Diego Puschini.
In Formal Methods for Components and Objects, 10th International Symposium FMCO 2011. State-of-the-Art Survey. Bernhard Beckert, Ferruccio Damiani, Frank de Boer, and Marcello Bonsangue, editors. volume 7542 of LNCS. Springer, 2013.
Mobile computing platforms need ever increasing performance, which implies an increase in the clock frequency applied to the processing elements (PE). As a consequence, the distribution of a single global clock over the whole circuit is tremendously dicult. Globally Asynchronous Locally Synchronous (GALS) designs alleviate the problem of clock distribution by having multiple clocks, each one being distributed on a small area of the chip. Energy consumption is the main limiting factor for mobile platforms as they are powered by batteries. Dynamic Voltage and Frequency Scaling (DVFS) in each Voltage and Frequency Island (VFI) has proven to be highly e ective to reduce the power consumption of the chip while meeting the performance requirements. Environmental parameters (i.e. temperature and supply voltage) changes also strongly a ect the chip performance and its power consumption. Some sensors can be buried in order to estimate via data fusion techniques the supply voltage and the temperature variations. For instance the knowledge of the gap between the temperature and its maximum value can be used to adapt the power management technique. The present paper deals with the design of a voltage and frequency management approach (DVFS) that explicitly takes into account the thermal constraints of the platform.
January 3rd, 2013 in
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Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, and Diego Melpignano.
In Formal Methods for Components and Objects, 10th International Symposium FMCO 2011. State-of-the-Art Survey. Bernhard Beckert, Ferruccio Damiani, Frank de Boer, and Marcello Bonsangue, editors. volume 7542 of LNCS. Springer, 2013.
PRO3D tackles two important 3D technologies, that are Through Silicon Via (TSV) and liquid cooling, and investigates their consequences on stacked architectures and entire software development. In particular, memory hierarchies are being revisited and the thermal impact of software on the 3D stack is explored. As a key result, a software design flow based on the rigorous assembly of software components and monitoring of the thermal integrity of the 3D stack has been developed. After 30 months of research, PRO3D proposes a complete tool-chain for 3D manycore, that integrates state-of-the-art tools ranging from system-level formal specifi cation and 3D exploration, to actual programming and runtime control on the 3D system. Current eforts are directed towards extensive experiments on an industrial embedded manycore platform.
January 3rd, 2013 in
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Pratyush Kumar and Lothar Thiele.
In Proceedings of the 33rd Real-Time Systems Symposium, RTSS 2012, San Juan, Puerto Rico, December 2012. IEEE.
For hard real-time systems, worst-case timing models are employed to validate whether timeliness properties, such as meeting deadlines, are always satis ed. We argue that such a deadline interface should be generalised in view of two separate motivations: (a) applications can tolerate bounded non-satisfaction of timeliness properties due to inherent ro- bustness or relaxed quality requirements, and (b) worst-case timing models do not expose the occurrence of certain rare yet predictable events. As a more expressive interface, we propose the Rare-Event with Settling-Time (REST) model wherein, during rare events nominal timing models can be violated up to a known bound. Such a violation may lead to non-satisfaction of the timeliness properties up to a certain bound. We characterise this bound in terms of (a) the longest interval when the deadlines are not met, which we call the settling-time, and (b) the maximum number of jobs that can miss deadlines during the settling-time called the overshoot. We propose two models of rare events, characterised on an interval domain. For a single stream of jobs, we provide methods to tightly compute the settling-time and overshoot. For multiple streams of jobs on a single processor, we show that amongst schedulers agnostic to the occurrence of the rare event, the EDF scheduler optimally minimises the settling-time. In contrast, RM is not optimal within the class of xed priority schedulers.
December 3rd, 2012 in
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