3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

David Cuesta, Jose L. Risco, Jose L. Ayala, David Atienza.
Proc. of 12th IEEE Latin-American Test Workshop (LATW11), IEEE Press, Beach of Porto de Galinhas, Brazil, March 27-30, 2011.
Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach; (2) an efficient Mixed Integer Linear Programming (MILP) representation of the floorplanning model; and (3) a smooth integration of the MILP model with an accurate thermal modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel’s SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system.