Rigorous System Level Modeling and Analysis of Mixed HW/SW Systems

Paraskevas Bourgos, Ananda Basu, Marius Bozga, Saddek Bensalem, Kai Huang, Joseph Sifakis.
MEMOCODE’11, July 2011, Cambridge, UK.
A grand challenge in complex embedded systems design is developing methods and tools for modelling and analysing the behaviour of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behaviour of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer) as the front-end for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority) as the modelling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture.