OpenMP-based HW Acceleration for On-Chip Multi-Core Shared-Memory Clusters

Andrea Marongiu, Paolo Burgio and Luca Benini.
Presented at the 1st Plateform 2012 Developper Conference, Grenoble, France.
Key to designing accelerator-based MPSoCs in a cost-effective manner is the availability of methodologies to quickly define and instantiate accelerators within a suitable architectural template, from both a hardware and a software perspective. By clearly defining such templates, and providing streamlined communication and synchronization mechanisms between processors and accelerators, programming models can be enriched with abstract constructs to allow designers to focus on accelerator specification at a high level. We present a vertically integrated HW/SW architecture, with a programming model and runtime support to design tightly coupled clusters including one or more dedicated accelerators named HW Processing Units (HWPU). The proposed approach includes an extended OpenMP programming API and compiler that allows the designer to mix code parallelization and acceleration mechanisms while hiding implementation details. Specifically, we extend OpenMP with a key custom directive to outline code regions which are to be hardware-accelerated, rather than executed in software.