Publications
The results and findings of PRO3D are published in :
- National and international journals;
- International and local conferences;
- Special issues of jrounals and chapters of edited books;
- International and national workshops and conferences.
There are currently 117 publications.
Borzoo Bonakdarpour, Marius Bozga, and Jean Quilbeuf.
Design Automation for Embedded Systems, pages 1-26, July 2012.
Model-based application development aims at increasing the application’s integrity by using models employed in clearly de ned transformation steps leading to correct-by-construction artifacts. In this
paper, we introduce a novel model-based approach for constructing correct distributed implementation of component-based models constrained by priorities. We argue that model-based methods are
especially of interest in the context of distributed embedded systems due to their inherent complexity (e.g., caused by non-deterministic nature of distributed systems). Our method is designed based on
three phases of transformation. The input is a model specified in terms of a set of behavioral components that interact through a set of high-level synchronization primitives (e.g., rendezvous and broadcasts) and priority rules for scheduling purposes. The first phase transforms the input model into a model that has no priorities. Then, the second phase transforms the deprioritized model into another model that resolves distributed conflicts by incorporating a solution to the committee coordination problem. Finally, the third phase generates distributed code using asynchronous point-to-point message passing primitives (e.g., TCP sockets). All transformations preserve the properties of their input model by ensuring observational equivalence. All the transformations are implemented and our experiments validate their effectiveness.
July 3rd, 2012 in
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S. Lesecq, L. Vincent, E. Beigne, and Ph Maurines.
In 12th International Forum on Embedded MPSoC and Multicore, July 9th-13rd, 2012, Quebec, Canada, July 2012. http://www.mpsoc-forum.org/previous/2012/index.htm
Today mobile computing platforms need ever-increasing computational performances while their energy consumption is drastically limited by battery lifespan. An optimal operating point is obtained thanks to a compromise between performance and power consumption. For distributed architectures, the supply voltage and the operating frequency of each processing element can be tuned dynamically to reach efficient performance/power consumption trade-offs. As a consequence, the physical state (e.g. actual supply voltage and temperature) of the integrated circuit must be monitored to locally adapt the chip parameters. A new method has been developed to estimate the supply voltage and temperature of a local area in an integrated circuit. The raw measurements are acquired form standard ring oscillators buried in the chip and the sensor fusion technique makes use of statistical tests.
July 3rd, 2012 in
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Pratyush Kumar, Dip oswami, Dipanjan Chakraborty, Kai Lampka, Anuradha Annaswamy, and Lothar Thiele.
In In Proceedings of the 49th Design Automation Conference, DAC 2012, San Fransisco, USA, June 2012. ACM
We propose a performance veri cation technique for cyber-physical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; there are multiple processor or electronic control unites (ECUs) communicating over buses like FlexRay and CAN. Current practice involves analyzing the architecture to estimate worst-case end-to-end message delays and using these delays to design the control applications. This involves a significant amount of pessimism since the worst-case delays often occur very rarely. We show how to combine functional analysis techniques with model checking in order to derive a delay-frequency interface that quantifies the interleavings between messages with worst-case delays and those with smaller delays. In other words, we bound the frequency with which control messages might su er the worst-case delay. We show that such a delay-frequency interface enables us to verify much tighter control performance properties compares to the what would be possibly only with worst-case bounds.
June 3rd, 2012 in
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Diego Melpignano, Luca Benini, Eric Flamand, Bruno Jego, Thierry Lepley, Germain Haugou, Fabien Clermidy, and Denis Dutoit.
In DAC 2012, pages 1137-1142.
P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-speci c HW IPs to the cluster. The rst P2012 SoC prototype in 28 nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18 mm2 with 2 W power consumption (worst-case). P2012 can run standard OpenCL™ and proprietary Native Programming Model SW components to achieve the highest level of control on application-to-resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs.
June 3rd, 2012 in
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Saddek Bensalem, Marius Bozga, Jean Quilbeuf, and Joseph Sifakis.
In Holger Giese and Grigore Rosu, editors, FMOODS/FORTE – Formal Techniques for Distributed Systems – Joint 14th IFIP WG 6.1 International Conference, FMOODS 2012 and 32nd IFIP WG 6.1 International Conference, FORTE 2012, Stockholm, Sweden, June 13-16, 2012. Proceedings, volume 7273 of Lecture Notes in Computer Science, pages 118-134. Springer, June 2012.
Distributed decentralized implementation of systems of communicating processes raises non-trivial problems. Correct execution of multiparty interactions, subject to priority rules, requires sophisticated mechanisms for runtime conflict detection and resolution. We propose a method for detection of false conflicts which combines partial observation of the system’s state and apriori knowledge extracted from invariants. We propose heuristics for determining optimal sets of observations leading to implementations with particular guarantees. We provide preliminary experimental results on an implementation of the method in the BIP framework.
June 3rd, 2012 in
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S. Lesecq, L. Vincent, E. Beigne, and Ph Maurines. Keynote at VARI 2012 the 3rd European Workshop on CMOS Variability, Nice, France. June 2012.
Today mobile computing platforms need ever-increasing computational performances while their energy consumption is drastically limited by battery lifespan. An optimal operating point is obtained thanks to a compromise between performance and power consumption. For distributed architectures (e.g. MultiProcessor System on Chip), the supply voltage and the operating frequency of each processing element are dynamically tuned to reach efficient performance/power consumption trade-offs. To increase the performance of each “actuator”, the physical state (e.g. its current supply voltage and temperature) of the integrated circuit must be monitored to locally adapt the control parameters. During this keynote, we will present a new estimation method based on statistical tests to estimate the supply voltage and the temperature of a local area in an integrated circuit. The raw measurements are acquired form standard ring oscillators buried in the chip and they are fused to estimate the IC physical state. Then we will show how this information might be used to fine-tune the control of the closed-loop actuators in order to ensure for these actuators the appropriate functioning, whatever the physical state in a given range.
June 3rd, 2012 in
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Y. Akgul, D. Puschini, S. Lesecq, I. Miro-Panades, P. Benoit, L. Torres, and E. Beigné.
In Faible Tension Faible Consommation (FTFC), 2012 IEEE, pages 1-4, June 2012.
Mobile computing platforms must provide ever increasing performances under stringent power consumption constraints. Dynamic Voltage and Frequency Scaling (DVFS) techniques allow to reduce the power consumption by providing just enough power to the chip in order to finish the task before its deadline. DVFS is usually achieved by setting the supply voltage and the clock frequency to predefi ned values (so-called “power modes”) during given durations that depend on the task to be run and on its deadline. Here, the problem of power management is recast as a linear programming one and the computation of the duration spent in each one of the N power modes is obtained with a Simplex algorithm solution. Results for 3 power modes exemplify the proposed approach.
June 1st, 2012 in
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Shivani Raghav, Andrea Marongiu, Christian Pinto, David Atienza, Martino Ruggiero, and Luca Benini.
In Proceeding of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units GPGPU-5, pages 101-109. ACM, May 2012.
Modern system-on-chips are evolving towards complex and heterogeneous platforms with general purpose processors coupled with massively parallel manycore accelerator fabrics (e.g. embedded GPUs). Platform developers are looking for efficient full-system simulators capable of simulating complex applications, middleware and operating systems on these heterogeneous targets. Unfortunately current virtual platforms are not able to tackle the complexity and heterogeneity of state-of-the-art SoCs. Software emulators, such as the open-source QEMU project, cope quite well in terms of simulation speed and functional accuracy with homogeneous coarse-grained multi-cores. The main contribution of this paper is the introduction of a novel virtual prototyping technique which exploits the heterogeneous accelerators available in commodity PCs to tackle the heterogeneity challenge in full-SoC system simulation. In a nutshell, our approach makes it possible to partition simulation between the host CPU and GPU. More specifically, QEMU runs on the host CPU and the simulation of manycore accelerators is offloaded, through semi-hosting, to the host GPU. Our experimental results confirm the flexibility and efficiency of our enhanced QEMU environment.
May 3rd, 2012 in
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Lars Schor, Iuliana Bacivarov, Hoeseok Yang, and Lothar Thiele.
In Proc. IEEE Latin American Test Workshop (LATW), Quito, Ecuador, April 2012. IEEE.
The reliability of multi-core systems is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. In real-time systems, high chip temperatures are even adherent to potential deadline violations. Therefore, correct functionality can only be guaranteed if the worst-case peak temperature is incorporated in real-time analysis. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core realtime system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighbouring cores and temperature-dependent leakage power. Finally, the proposed method is applied to a multicore ARM platform to validate its efficiency and accuracy.
April 3rd, 2012 in
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Lars Schor, Iuliana Bacivarov, Hoeseok Yang, and Lothar Thiele.
In In Proc. of the 18th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2012, Beijing, China, April 2012. IEEE Computer.
Due to increased on-chip power density, multi-core systems face various thermal issues. In particular, exceeding a certain threshold temperature can reduce the system’s performance and reliability. Therefore, when designing a real-time application with non-deterministic workload, the designer has to be aware of the maximum possible temperature of the system. This paper proposes an analytic method to calculate an upper bound on the worst-case peak temperature of a realtime system with multiple cores generated under all possible scenarios of task executions. In order to handle a broad range of uncertainties, task arrivals are modeled as periodic event streams with jitter and delay. Finally, the proposed method is applied to a multi-core ARM platform and our results are validated in various case studies.
April 3rd, 2012 in
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